The present invention generally relates to semiconductor packages and more particularly to semiconductor packages and methods of making Dual Flat Non-Leaded (DFN) semiconductor packages having reduced electrical resistance and improved thermal properties.
Quad Flat Non-Leaded (QFN) semiconductor packages are well known in the art. QFN semiconductor packages are widely used in high pin out IC package applications. For example, a QFN semiconductor package is disclosed in U.S. Patent Application Publication 2002/0177254 entitled “Semiconductor Package and Method for Making the Same”. The disclosed semiconductor package includes a plurality of connection pads and an embedded die. The connection pads at least partially enclose a die receiving area. An insulator is disposed in the die receiving area and the die is attached to the insulator. The die has a plurality of die bond pads. A plurality of connectors connect the die bond pads to respective connection pads. An encapsulant at least partially encapsulates the connection pads, insulator and die. The connection pads and insulator have exposed surfaces on an outer surface of the encapsulant. The exposed surfaces are substantially co-planar with the outer surface of the encapsulant. A resulting semiconductor package is shown in FIG. 1A and FIG. 1B.
It has been proposed to use DFN semiconductor packages in power MOSFET applications. In power MOSFET applications a major concern relates to thermal and electrical performance. The total electrical resistance Rds(on) of an electrical component includes chip resistance and package resistance. Chip resistance depends upon the wafer process technology used to fabricate the chip and die size while package resistance depends upon the quantity, diameter and length of bond wires used to bond internal chip bonding areas to external package leads. By increasing the amount of bond wires and/or their diameters, total Rds(on) can be reduced dramatically. QFN and DFN packages of the prior art suffer from the disadvantage of having high Rds(on).
A prior art 6×5 mm DFN package 700 is shown in FIG. 7. A leadframe 710 includes a narrow source bonding area 720 and a narrow gate bonding area 730. The narrow source bonding area 720 of DFN package 700 allows for only 11 narrow and short bonding wires 760 for connecting source leads 735 to a semiconductor die 750 and consequently does not provide reduced Rds(on).
There is therefore a need in the art for a DFN semiconductor package having improved electrical performance and thermal properties. Preferably such a DFN semiconductor package provides for reduced electrical resistance and inductance and improved thermal dissipation.